1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating an electrostatic discharge (ESD) protection circuit to protect an integrated circuit with a property of low punch-through voltage.
2. Description of Related Art
In the fabrication of an integrated circuit (IC) device, such as dynamic random access memory (DRAM) or statistic random access memory (SRAM), ESD is one of the main factors causing IC damage. For example, when one walks on a carpet with semi-conductor wafers, if relative humidity (RH) is high, an electrostatic voltage of about a few hundred volts may exist on one's body and wafers. If the RH is very low, the electrostatic voltage may be even as high as about a few thousand volts. If a conductive object occasionally contacts the wafers, a strong ESD could occur and damage the ICs on the wafers. ESD is an especially serious problem for fabrication of a complementary metal-oxide semiconductor (CMOS) device.
In order to protect wafers from ESD damage, many methods to solve the ESD problem have been proposed. The most common conventional method is to make an ESD protection circuit between input/output (I/O) pads and internal circuits so that the ESD does not damage the ICs fabricated on the wafers. Currently, the ESD problem is one of main factors causing damage to the IC device at deep sub-micron level. It is very desired to have an ESD protection circuit, which can effectively protect IC devices from ESD damage.
Moreover, a thinner gate oxide layer is necessary as the device integration increases. This causes that a gate-oxide breakdown voltage is approaching to a junction breakdown voltage of a field effect transistor or even less. In this situation, performance of the original ESD protection circuit is degraded. In addition, a circuit architecture is usually designed by minimum design rules, in which a sufficient distance between a contact and a diffusion-region edge, or a contact and a gate edge is not properly considered and designed. This causes that devices in high integration have poor performance to resist a huge electrostatic transient current and wafers is therefore damaged by the ESD phenomenon.
Typically, the ESD protection is done by a conventional ESD protection circuit including a coupling-type diode or a coupling-type metal-oxide semiconductor (MOS) device. However, both are very power consuming and cannot endure a larger ESD stress. The gate-oxide thickness becomes small as device integration gets high, resulting in a low gate-oxide breakdown voltage. IF the gate-oxide breakdown voltage is as low as about the source/drain junction breakdown voltage, the ESD protection ability is severely degraded.
FIGS. 1A-1D are cross-sectional views, schematically illustrating a conventional fabrication process to form an ESD protection circuit.
In FIG. 1A, an isolation structure 12 is formed on a semiconductor substrate 10 so as to form active regions respectively at a device region 14 for a desired IC device and a protection circuit region 16 for an ESD protection device. The isolation structure 12 can be a field oxide (FOX) structure or a shallow trench isolation (STI) structure. A MOS transistor 18 and a MOS transistor 20 are respectively formed at the device region 14 and the protection circuit region 16. The MOS transistor 18 includes a gate oxide layer 22, a polysilicon gate 24, a spacer 26, and a channel source/drain region 28 with a lightly doped drain (LDD) structure, which includes, for example and N.sup.+ region and an N.sup.- doped region. The MOS transistor 20 includes a gate oxide layer 30, a polysilicon gate 32, a spacer 34, and a source/drain region 36 with a lightly doped drain (LDD) structure, which includes, for example, and N.sup.+ region and an N.sup.- region.
In FIG. 1B, a photoresist layer 38 is formed over the substrate 10 to cover the device region 14. Using wet etching, the spacer 34 on each sidewall of the polysilicon gate 32 is removed.
In FIG. 1C, at the current stage, the source/drain region 36 at the protection circuit region 16 is exposed. An ion implantation process is performed with a heavy N.sup.+ concentration so as to form a source/drain region 36a, in which the LDD structure has been merged away.
In FIG. 1D, the photoresist layer 38 is removed. A spacer 40 is formed on each sidewall of the polysilicon gate 32 by thermal oxidation and etching back. A self-aligned silicide (Salicide) process is performed to form several Salicide layers 42, 43, 44, and 45 on the exposed surface of the source/drain region 28, 36a and the polysilicon gates 24, 32.
A further fabrication process to accomplish the device is well known by the one skilled in the art, and is not further described here.
In the above conventional fabrication process, the IC device and the ESD protection device are simultaneously formed. In this conventional ESD protection structure, the source/drain region 36a is heavily doped with N-type dopants so as to reduce junction resistance and to allow the power consumption rate to be evenly distributed. However, the junction breakdown voltage still cannot be reduced. As a result, the conventional ESD device cannot effectively protect the internal IC device with a gate-oxide thickness of about 35 angstroms or less.